1. Field of the Invention
Example embodiments of the present invention relate to a capacitor and a method of manufacturing the capacitor. More particularly, example embodiments of the present invention relate to a capacitor having a protection structure and a method of manufacturing the capacitor.
2. Description of the Related Art
Recently, semiconductor devices have higher response speed, larger storage capacity, and/or lower power consumption and information processing devices, which incorporate the semiconductor devices, have been widely used. The semiconductor devices may be generally divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices may include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. In general, a volatile semiconductor memory device, for example, a DRAM device, has a capacitor and a switching element, for example, a transistor.
A polysilicon-insulator-polysilicon (PIP) capacitor has been employed in semiconductor memory devices. A PIP capacitor may be easily formed because polysilicon is relatively stable at a high temperature. In addition, manufacturing technology for capacitors, for example, a chemical vapor deposition (CVD) process, has become highly developed. However, electrical characteristics of the PIP capacitor may vary in accordance with an applied voltage. Particularly, because a lower electrode and an upper electrode of the PIP capacitor are made of polysilicon, depletion layers may be formed between the upper electrode and an insulation layer and between the insulation layer and the lower electrode. When the depletion layers are formed in the PIP capacitor, a thickness of a dielectric layer may relatively increase, which may cause the PIP capacitor to have a deteriorated capacitance. In particular, if the PIP capacitor is used for highly integrated semiconductor device having a design rule of below about 90 nm, the semiconductor device may not have the desired capacitance.
Considering the above-disclosed disadvantages of a PIP capacitor, a metal-insulator-metal (MIM) capacitor has been developed. In a method of manufacturing a conventional MIM capacitor, an insulating interlayer may be formed on a substrate, and a contact pad may be formed through the insulating interlayer. The contact pad may be formed using doped polysilicon, because metal may melt or diffuse into the substrate at relatively high temperatures in proceeding process steps. A metal cylindrical lower electrode may be formed on the contact pad. Here, galvanic coupling may be generated between the lower electrode and the polysilicon contact pad. Galvanic coupling may be generated between two different conductive material layers or patterns. When the galvanic coupling is formed between two different conductive layers or patterns, one of the conductive layers or patterns may erode. If galvanic coupling is generated between the lower electrode and the polysilicon contact pad, the polysilicon in the contact pad may be rapidly eroded by chemicals used in proceeding etching processes. As a result, a void may be formed between the contact pad and the lower electrode because the contact pad may be rapidly etched in an etching process.
FIG. 1 is a cross-sectional view illustrating a void formed in a contact pad electrically connected to a prior art capacitor.
Referring to FIG. 1, the prior art capacitor may include a lower electrode 18 positioned on a contact pad 14, a dielectric layer 20 formed on the lower electrode 18, and an upper electrode 22 formed on the dielectric layer 20. The contact pad 14 may make contact with a contact region 12 formed in a substrate 10.
When a void 16 is formed in the contact pad 14, the resistance between the contact pad 14 and the lower electrode 18 may increase such that an electrical failure may occur in the capacitor. Additionally, the contact pad 14 may not be capable of supporting the lower electrode 18, if the size of the void 16 is relatively large. Hence, the capacitor may fall over toward the substrate 10.
To overcome the above-described problems, a method of manufacturing a capacitor by minimizing permeation of chemicals has been suggested. In this method, the permeation of a wet etching solution may be prevented by a plasma nitrification treatment around a sidewall of a concave groove formed on a mold layer. However, even though nitrogen atoms are introduced onto the surface of the concave groove through the plasma nitrification treatment, the permeation of the wet etching solution may not be completely blocked, and the wet etching solution may still permeate into a contact pad and a lower electrode. Additionally, if only the sidewall of the concave groove is nitrified, the wet etching solution may still permeate into the contact pad positioned under the lower electrode.
According to another prior art method, an oxide mold layer may be formed on a first barrier layer and a second barrier layer, and a contact hole may be formed through the oxide mold layer. After a third barrier layer is formed on a sidewall of the contact hole, a ruthenium lower electrode may be formed in the contact hole. Because the barrier layers may be of conductive titanium nitride, the barrier layers should be removed by additional processes. However, portions of the barrier layers may remain, which may cause electrical failure between adjacent capacitors. Further, etching gases used to remove the titanium nitride layer may attack the contact pad causing damage to the contact pad.